Overview
Description
Double the drive of the standard 97U877 device. Low skew, low jitter PLL clock driver. 1 to 5 differential clock distribution (SSTL_18)
Features
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Auto PD when input signal is at a certain logic state
Comparison
Applications
Documentation
Featured Documentation
Log in required to subscribe
|
|
|
|
|---|---|---|
| Type | Title | Date |
| Datasheet | PDF 313 KB | |
| End Of Life Notice | PDF 536 KB | |
2 items
|
||
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Product Options
Applied Filters: