This video describes the challenges of trying to measure a source-terminated clock at the end of a transmission line when an SOC is present on the board. Due to the additional resistance of the bond wires, you may see a step on the rising and falling edges of the waveform when you measure at the pin of the SoC. To get a good measurement at the end of the transmission line, it is recommended to remove the SoC from the board, and then take the measurement at the PCB pin pad.

Presented by Ron Wade, timing expert at IDT. For more information about IDT's leading portfolio of clock and timing ICs, visit www.idt.com/products/clocks-timing.