The ISL70001SEH, ISL70001SRH are radiation hardened and SEE hardened high efficiency monolithic synchronous buck regulators with integrated MOSFETs. This single-chip power solution operates over an input voltage range of 3V to 5.5V and provides a tightly regulated output voltage that is externally adjustable from 0.8V to ~85% of the input voltage. Output load current capacity is 6A for TJ < +145 °C. High integration and class-leading radiation tolerance make the ISL70001SEH, ISL70001SRH ideal choices to power many of today’s small form factor applications. Two devices can be synchronized to provide a complete power solution for large-scale digital ICs, like field-programmable gate arrays (FPGAs) that require separate core and I/O voltages. In applications where the ENABLE input is tied high to PVIN we recommend that the input voltage ramp rate be equal to or greater than 10V/ms. This is to prevent unwanted voltage from prematurely appearing on the output. For a PVIN voltage that has a slower ramp rate or is stepped up we recommend use of the ISL70001ASEH. Ensuring that the ENABLE input is held low until the chosen VINPOR is satisfied will prevent this ‘false start’.


  • ±1% reference voltage over line, load, temperature, and radiation
  • Current mode control for excellent dynamic response
  • Full Mil-temp range operation (TA = -55 °C to +125 °C)
  • High efficiency >90%
  • Fixed 1MHz operating frequency
  • Available in a thermally enhanced heatsink package - R48.B
  • Operates from 3V to 5.5V supply
  • Adjustable output voltage
  • Two external resistors set VOUT from 0.8V to ~85% of VIN
  • Bidirectional SYNC pin allows two devices to be synchronized 180° out-of-phase
  • Starts into prebiased load
  • Power-good output voltage monitor
  • Adjustable analog soft-start
  • Input undervoltage, output undervoltage and output overcurrent protection
  • Electrically screened to DLA SMD 5962-09225
  • QML qualified per MIL-PRF-38535 requirements
  • EH version is wafer-by-wafer acceptance tested for ELDRS
  • Radiation hardness
  • Total dose [50-300rad(Si)/s]: 100krad(Si) (min)
  • Total dose [<10mrad(Si)/s]: 50krad(Si) (min)
  • SEE hardness
  • SEL and SEB LETeff: 86.4MeV/mg/cm2 (min)
  • SEFI X-section (LETeff = 86.4MeV/mg/cm2) 1.4 x 10-6 cm2 (max)
  • SET LETeff (<1 pulse perturbation) 86.4MeV/mg/cm2 (min)




  • FPGA, CPLD, DSP, CPU core or I/O voltages
  • Low-voltage, high-density distributed power systems


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