The 72V3611 is a 64 x 36 3.3V Sync FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. Communication between each port can take place through two 36-bit mailbox registers. Two or more devices may be used in parallel to create wider data paths. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.


  • Free-running CLKA and CLKB may be asynchronous or coincident
  • Synchronous data buffering from Port A to Port B
  • Mailbox bypass register in each direction
  • Programmable Almost-Full (AF) and Almost-Empty (AE) flags
  • Microprocessor Interface Control Logic
  • Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA
  • Empty Flag (EF) and Almost-Empty (AE) flags synchronized by CLKB
  • Passive parity checking on each Port
  • Parity Generation can be selected for each Port
  • Available in 132-pin PQFP and 120-pin TQFP packages
  • Industrial temperature range (–40C to +85C) is available




Design & Development