The 72V225 is a 1K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72225 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.


  • 10 ns read/write cycle time
  • 5V input tolerant
  • IDT Standard or First Word Fall Through timing
  • Single or double register-buffered Empty and Full flags
  • Easily expandable in depth and width
  • Asynchronous or coincident Read and Write Clocks
  • Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings
  • Half-Full flag capability
  • Output enable puts output data bus in high-impedance state
  • Available in 64-pin TQFP and STQFP packages
  • Industrial temperature range (–40C to +85C) is available




Design & Development