The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.


  • Optimal combination of large capacity, design flexibility and small footprint
  • Ideal for prioritization, bidirectional, and width expansion applications
  • 10 ns read/write cycle time
  • Separate control lines and data lines for each FIFO
  • Separate Empty, Full, Programmable Almost-Empty and Almost- Full flags for each FIFO
  • Enable puts output data lines in high-impedance state
  • Available in 64-pin TQFP and STQFP packages
  • Industrial temperature range (–40C to +85C)




Design & Development