Asynchronous FIFOs

About Asynchronous FIFO Devices

Asynchronous FIFOs are a type of data buffer, where the first byte to arrive at the input is the first to leave at the output. In a computer system, the operating system’s algorithm schedules CPU time for each process according to the order in which it is received. An asynchronous FIFO will queue the data and release it in a sequential fashion.

Renesas asynchronous FIFOs are typically used for the synchronization of CPU and other computer hardware. FIFOs are generally implemented as a circular queue, and thus have a read and write pointer. Synchronous FIFOs use clocks for reading and writing, while asynchronous FIFOs are usually controlled by asynchronous signals.

Key parameters for choosing an asynchronous FIFO include:

• Core voltage: The supply voltage used to power the device. This is typically defined by the power rails available in the system.
• I/O voltage: The voltage used for the data input and output, for some devices this is separate from the core voltage.
• Density: This is the number of bits the asynchronous FIFO will hold in its register. Renesas offers sizes up to 512Kb.
• Bus width: The number of “lanes” used to read and write to the device. Renesas offers all popular configurations.
• Access time: The time it takes to read the next bit from the device. Ideally, the access time of the asynchronous FIFO should be fast enough to keep up with the CPU. If not, the CPU will waste a certain number of clock cycles, which makes it slower. Renesas offers access times down to 12ns.