Overview

Description

The IDT2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on the IDT proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or directly from the input (for testing), and can be set to tri-state mode or to stop at a low level. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The IDT2305 is available in two different versions. The IDT2305-1 is the base part. The IDT2305-1H is a high drive version with faster rise and fall times.

Features

  • Clock outputs from 10 to 133 MHz
  • Zero input-output delay
  • Four low skew (<250 ps) outputs
  • Device-to-device skew <700 ps
  • Full CMOS outputs with 25 mA output drive capability at TTL levels
  • 5 V tolerant CLKIN
  • Tri-state mode for board-level testing
  • Advanced, low power, sub-micron CMOS process
  • Operating voltage of 3.3 V
  • Industrial temperature range available
  • Packaged in 8-pin SOIC

Documentation

Type
Date
PDF 210 KB Datasheet
PDF 187 KB Application Note
PDF 91 KB Application Note
PDF 1.99 MB Application Note
PDF 217 KB Overview
PDF 606 KB End Of Life Notice
PDF 599 KB End Of Life Notice
PDF 322 KB Application Note
PDF 611 KB Product Change Notice
PDF 611 KB Product Change Notice
PDF 596 KB Product Change Notice
PDF 544 KB Product Change Notice
PDF 170 KB Application Note
PDF 495 KB Application Note
PDF 442 KB Application Note
PDF 153 KB Application Note
PDF 565 KB Application Note
PDF 223 KB Product Change Notice
PDF 298 KB Product Change Notice
19 items

Design & Development

Software & Tools

Software Downloads

Type Date
PDF 606 KB End Of Life Notice
PDF 599 KB End Of Life Notice
2 items

Models

Models

Type Date
ZIP 24 KB Model - IBIS
ZIP 86 KB Model - SPICE
2 items

Support