Renesas' leading RF timing portfolio consists of devices designed for exceptionally low phase noise and spurious performance. The RF-PLL-based devices support radio unit synchronization, jitter attenuation, the generation of JESD204B/C compliant clock signals, and the synthesis of local oscillator clocks. RF buffers with very low additive phase noise complement the PLL-based devices with signal distribution functions.
The industry's first single-chip radio synchronization devices integrate digital PLLs (DPLLs) with a high-performance RF-PLL. With support for Precision Timing Protocol (PTP, IEEE 1588), synchronous Ethernet and JESD204B/C, the devices simplify the design of highly accurate frequency and phase synchronization for wireless infrastructure radios. The devices implement frequency generation and clock jitter attenuation of multiple, independent frequency domains, for instance, physical layer Ethernet and JESD204B/C compliant radio clocks. Supported synchronization standards include IEEE 1588-2019 and ITU-T Synchronous Ethernet (SyncE) with compliance to ITU-T G.8273.2 Class C as part of Telecom Time Slave Clock (T-TSC) and G8262.1 enhanced Synchronous Equipment Clock (eSEC). The integrated RF-PLL generates multiple low-phase noise and low-spurious clocks as the reference to DAC/ADC circuits for achieving the best possible ADC/DAC conversion. For synchronizing frequency, phase and time of day, 1PPS input signals can be used. Devices are also suitable as PTP hardware clocks where the phase is set by an external IEEE 1588 software stack or controlled directly by a software servo as a DCO. The frequency translation capabilities include a wide range of input and output frequencies.
Renesas offers high-performance JESD204B/C jitter attenuators for applications needing the generation and phase management of low phase noise clocks. The devices are typically used as a central, JESD204B/C compliant source of clock and SYSREF signals for integrated and stand-alone A/D and D/C converter circuits. A dual-stage PLL architecture supports both jitter attenuation and frequency generation. With capabilities of up to 6GHz clock frequencies, phase noise less than 80fs RMS and a spurious attenuation of 90dB, the devices enable the best possible system performance in any data sampling application. High signal fanout, flexible differential I/O, signal phase manipulation functions, and input monitoring/switching functions complement the exceptional AC performance.
RF synthesizers generate one or two RF reference clock signals over a wide, configurable and continuous frequency range. The internal PLL uses fractional or integer feedback supporting applications with varying clock frequency needs. The desired output frequency is digitally set by a serial interface. Output phase noise is as low as 35fs RMS (integer feedback) and 66fs RMS (fractional feedback). The highest support output frequency is 18GHz. RF synthesizers are typically used in radio applications as a reference clock device for up/down converter circuits and in data sampling applications as a flexible frequency source for ADC/DAC devices.
Supporting frequencies up to 3000MHz, Renesas' RF buffers extend the fanout of radio synchronizers, JESD204B/C clock jitter attenuators and RF synthesizers. The single and dual-channel RF buffers use silicon-germanium (SiGe) technology to minimize additive phase noise and variations of the propagation delay over temperature. Renesas offers the world’s first RF buffers fully supporting high-speed JESD204B/C clocking. The RF buffers feature independent signal paths for device clocks and synchronization signals (SYSREF). Configurable phase delay, frequency dividers and multi-chip phase synchronization provide maximum system and board design flexibility. This is combined with extremely low additive phase noise, high-frequency capability, and low output skew and superior channel isolation.
JESD204B/C clocks are used in systems that implement the JESD204B and JESD204C high-speed serial interface. Now in its fourth iteration, the JESD204C standard defines a maximum lane rate up to 32Gbps per channel, with support for harmonic frame clocking and deterministic latency. In previous versions of JESD204, the frame clock was the absolute timing reference in the system. Typically, both the frame clock and the data converter sampling clocks were the same, which limited the flexibility of the system and made multi-device synchronization very complex. In JESD204B/C, the device clock is the timing reference for each device in the system. The Renesas JESD204B/C clock jitter attenuators and radio synchronizers provide a high-quality source for these timing signals, resulting in exceptional system performance and reliability.
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This video introduces the industry’s first fully-integrated synchronizer for 5G enhanced common public radio interface (eCPRI) radio synchronization.
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