The device is a 4-output PCIe clock fanout buffers for PCIe Gen1–5 applications. It has an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock.
 
For information regarding evaluation boards and material, please contact your local sales representative.
 

Features

  • Intergrated terminations
    • 85Ω transmission lines require 0 termination resistors  
    • 100Ω transmission lines require only 2 series resistors per output
  • OE pin for each output supports CLKREQ# applications
  • Intelligent power-down mode when all OE# pins are high (all outputs off)
  • Spread-spectrum tolerant
  • Open drain LOS# output indicates a loss of the input clock and returns the outputs to a Low/Low state
  • Flexible power sequencing: Input clock is internally biased so a floating input clock will not inject noise into system
  • Power Down Tolerant: Control inputs will not clamp to ground or VDD if a signal is applied before chip VDD is applied
  • Space saving 4 × 4 mm 20-VFQFPN
  • Easy AC-coupling to other logic families; see application note AN-891.

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Buy Sample
9DBL0455NLGI
Active VFQFPN 20 I 85 Tray
Availability
9DBL0455NLGI8
Active VFQFPN 20 I 85 Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9DBL0255_0455 Datasheet Datasheet PDF 297 KB
Application Notes & White Papers
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
Product Change Notice PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
Product Change Notice PDF 5.61 MB
Downloads
9DBL0455 IBIS Model Model - IBIS ZIP 16 KB
Other
9DBL0455 Reference Schematic Schematic PDF 116 KB
PCI Express Timing Solutions Overview Overview PDF 275 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB