Clocks & Timing

Overview

The 9FGV0641 is a member of IDT's SOC-Friendly 1.8V Very-Low-Power PCIe clock family. The device has integrated 100 ohm output terminations providing direction connection to 100 ohm transmission lines. The device also has 6 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

9FGV0641 Block Diagram
9FGV0641 Pinout Diagram
9FGV0641 Block Diagram
9FGV0641 Pinout Diagram
  • PCIe Gen1–4 compliant
  • LP-HCSL outputs with integrated terminations; save 24 resistors compared to standard PCIe devices
  • 54 mW typical power consumption; reduced thermal concerns
  • Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
  • OE# pins; support DIF power management
  • Programmable slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • DIF outputs blocked until PLL is locked; clean system start-up
  • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI
  • External 25 MHz crystal; supports tight ppm with 0 ppm synthesis error
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface works with legacy controllers
  • Space saving 5x5 mm 40-pin VFQFPN; minimal board space
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment
Multi-Display HMI SoM
High-Performance HMI System
High-Performance HMI System
Scalable HMI SMARC SoM with AI
Wireless Network Video Recorder
Wireless Digital Signage

Documentation

Title
Type 		Date
9FGV0641 Datasheet
PDF 542 KB 		Datasheet
AN-805 Recommended Ferrite Beads
PDF 91 KB 		Application Note
PCN# : 220015 (R1) Add Alternate Assembly Location on VFQFPN Packages
PDF 734 KB 		Product Change Notice
PCN# : 220015 Add Alternate Assembly Location on VFQFPN Packages
PDF 728 KB 		Product Change Notice
PCI Express Timing Solutions Overview
PDF 2.40 MB 		Overview
AN-827 Application Relevance of Clock Jitter
PDF 1.99 MB 		Application Note
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility
PDF 983 KB 		Product Change Notice
Timing Products for NXP (Freescale) i.MX
PDF 321 KB 简体中文 		Guide
AN-975 Cascading PLLs
PDF 255 KB 		Application Note
AN-918 Programmable Clocks vs Crystal Oscillators
PDF 307 KB 		Application Note
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs
PDF 480 KB 		Application Note
9FGx08 PCIe Clock Generator Evaluation Boards User Guide
PDF 838 KB 		Manual - Hardware
AN-879 Low-Power HCSL vs Traditional HCSL
PDF 235 KB 		Application Note
AN-843 PCI Express Reference Clock Requirements
PDF 1.90 MB 		Application Note
AN-842 Thermal Considerations in Package Design and Selection
PDF 495 KB 		Application Note
AN-840 Jitter Specifications for Timing Signals
PDF 442 KB 		Application Note
AN-839 RMS Phase Jitter
PDF 233 KB 		Application Note
AN-835 Differential Input with VCMR being VIH Referenced
PDF 160 KB 		Application Note
AN-836 Differential Input to Accept Single-ended Levels
PDF 120 KB 		Application Note
AN-815 Understanding Jitter Units
PDF 565 KB 		Application Note
PCN# : TB1311-01 New Carrier Tape on VFQFPN-28, VFQFPN-40, VFQFPN-48
PDF 790 KB 		Product Change Notice
AN-802 Crystal-Measuring Oscillator Negative Resistance
PDF 136 KB 		Application Note
22 items

Design & Development

Software Downloads

Title
Type Date
Software for PCIe Evaluation Kits
ZIP 440 KB 		Software & Tools - Evaluation Software
1 item

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Models

Title
Type Date
9FGV0641 IBIS Model
ZIP 95 KB 		Model - IBIS
1 item

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    9FGV0641AKILF
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    view_in_ar
    Samples Available
    		 VFQFPN 40 I Yes Tray Get Samples,
    9FGV0641AKILFT
    play_circleActive
    memory
    view_in_ar
    		VFQFPN 40 I Yes Reel
    9FGV0641AKLF
    play_circleActive
    memory
    view_in_ar
    Samples Available
    		 VFQFPN 40 C Yes Tray Get Samples,
    9FGV0641AKLFT
    play_circleActive
    memory
    view_in_ar
    		VFQFPN 40 C Yes Reel
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    • Cart icon to the right of the chip icon: Indicates that samples are available for this product

    Support

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    Clocks & Timing FAQs
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    Renesas Samples

    Select an orderable part number:

    Orderable Part ID Sample
    9FGV0641AKILF
    Availability
    Add to request
    9FGV0641AKLF
    Availability
    Add to request
    PCIe Reference Clock Jitter Budgets

    IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

    Video List
    PCIe Reference Clock Jitter Budgets
    PCIe Data Rates vs Clock Jitter Specs
    What Does PCIe Gen5 Say About SRIS?
    PCI Express (PCIe) Clock Overview by IDT
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
    IDT Timing Solutions for NXP QorIQ / Layerscape CPU
    Overview of Timing Requirements for NXP QorIQ LS Processors
    Standard HCSL vs. Low-Power HCSL (LP-HCSL) Output Signaling
    PCI Express (PCIe) Clock Generators by IDT
    PCI Express (PCIe) Clock Applications Overview by IDT
    PCI Express Gen 1 to Gen 4/Gen 5 Data Rate Evolution
    PCI Express Gen 1 to Gen 4/Gen 5 Clock Specification Evolution
    PCI Express Common Clock Jitter Model and Transfer Functions

    News & Blog Posts

    Solving Common Issues with Respect to PCIe Timing Design on the Modern Server System Blog Post Apr 14, 2022
    Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications Blog Post May 22, 2018
    IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices News Apr 30, 2018
    IDT Announces World’s Lowest-power PCI Express Timing Family News Aug 16, 2012