9FGL08

Clocks & Timing

Overview

The 9FGL0841/51 devices are 8-output 3.3V PCIe Gen1–5 clock generators. Each output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. Two different spread spectrum levels, in addition to spread off, are supported. The 9FGL0841/51 supports PCIe Gen1–5 Common Clocked architectures (CC), PCIe Separate Reference no-Spread (SRNS) and Separate Reference Independent Spread (SRIS) clocking architectures.

For information regarding evaluation boards and material, please contact your local sales representative.

PCIe Gen1–5 CC-compliant
Supports PCIe SRIS and SRNS clocking
Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
Pin-selectable SRnS 0%, CC 0% and CC/SRIS -0.5% spread
SMBus-selectable CC/SRIS -0.25% spread
One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support
Easy AC-coupling to other logic families, see application note AN-891.
Space saving 6 × 6 mm 48-VFQFPN

Genoa Server Solution

Documentation

Title	Type	Date
9FGL02x1-04x1-06x1-08x1D Family Datasheet PDF545 KB	Datasheet	Jun 14, 2022
AN-827 Application Relevance of Clock Jitter PDF1.99 MB	Application Note	Mar 1, 2022
AN-975 Cascading PLLs PDF255 KB	Application Note	Aug 2, 2017
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs PDF480 KB	Application Note	Dec 11, 2015
AN-879 Low-Power HCSL vs Traditional HCSL PDF235 KB	Application Note	Apr 8, 2015
AN-843 PCI Express Reference Clock Requirements PDF1.90 MB	Application Note	May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection PDF495 KB	Application Note	May 12, 2014
AN-840 Jitter Specifications for Timing Signals PDF442 KB	Application Note	May 8, 2014
AN-839 RMS Phase Jitter PDF233 KB	Application Note	May 7, 2014
AN-835 Differential Input with VCMR being VIH Referenced PDF160 KB	Application Note	May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels PDF120 KB	Application Note	May 6, 2014
AN-815 Understanding Jitter Units PDF565 KB	Application Note	Apr 24, 2014
AN-802 Crystal-Measuring Oscillator Negative Resistance PDF136 KB	Application Note	Mar 12, 2014
AN-805 Recommended Ferrite Beads PDF121 KB	Application Note	Jan 15, 2014
9FGL02x1-04x1-06x1-08x1 Family Datasheet PDF482 KB	Datasheet	Jun 2, 2022
Timing Products for NXP (Freescale) i.MX PDF321 KB 简体中文	Guide	Nov 1, 2018
9FGx08 PCIe Clock Generator Evaluation Boards User Guide PDF838 KB	Manual - Hardware	Oct 27, 2015
PCI Express Timing Solutions Overview PDF2.40 MB	Overview	Apr 8, 2022
IDT Clock Generation Overview PDF1.83 MB	Overview	Apr 29, 2016
PCN# : 220011 (R1) New Revision for 9FGL/9DBL Family PDF120 KB	Product Change Notice	Jul 26, 2022
PCN# : 220011 New Revision for 9FGL/9DBL Family PDF119 KB	Product Change Notice	Jun 16, 2022
PCN# : 220015 Add Alternate Assembly Location on VFQFPN Packages PDF728 KB	Product Change Notice	May 13, 2022
PCN# : TP1910-02 Metal Change to Enhance Spread Performance PDF127 KB	Product Change Notice	Oct 15, 2019
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility PDF983 KB	Product Change Notice	Jun 25, 2019
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location PDF583 KB	Product Change Notice	Dec 20, 2016
PCN# : MM1610-01 Improve performance to meet the new PCIe PDF23 KB	Product Change Notice	Oct 11, 2016
9FGL08xx EVB Reference Schematic PDF34 KB	Schematic	Jan 30, 2019

Design & Development

Software Downloads

	Title	Type	Date
	Software for PCIe Evaluation Kits ZIP440 KB	Software & Tools - Evaluation Software	Mar 24, 2018

Boards & Kits

EVK9FGL0841

Evaluation

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Evaluation Board for the 100ohm 9FGL0841 PCIe Clock Generator

This is the evaluation board for the 9FGL0841 clock generator.

EVK9FGL0851

Evaluation

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Evaluation Board for the 85ohm 9FGL0851 PCIe Clock Generator

This is the evaluation board for the 9FGL0851 clock generator.

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Product Options

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Product Options

Part Number (4) Active (8) Obsolete / NRND / LTB	Pkg. Type VFQFPN Logical Operator	Lead Count (#)	Temp. Grade I Logical Operator	Output Impedance 85 100 Logical Operator	Carrier Type Reel Tray Logical Operator	Buy / Sample Buy / Quote Get Samples Logical Operator

Support

Contact Technical Support Get Samples Clocks & Timing FAQs Clock Tree Design Service RenesasRulz Clocks & Timing Forum

Orderable Part ID	Sample
9FGL0841CKILF	Availability Add to cart
9FGL0851CKILF	Availability Add to cart

Videos & Training

PCIe Reference Clock Jitter Budgets

IDT’s chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.

Video List

PCIe Reference Clock Jitter Budgets

PCIe Data Rates vs Clock Jitter Specs

What Does PCIe Gen5 Say About SRIS?

PCI Express (PCIe) Clock Overview by IDT

PCIe Clocking Architectures (Common and Separate)

PCIe Common Clock Architecture and its Impact on Clocking

PCIe Separate Reference without Spread Clock Architecture

PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview

IDT Timing Solutions for NXP QorIQ / Layerscape CPU

Overview of Timing Requirements for NXP QorIQ LS Processors

Standard HCSL vs. Low-Power HCSL (LP-HCSL) Output Signaling