Clocks & Timing

Overview

The 82P33741 Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet provides tools to manage timing references, clock conversion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock generation; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

82P33741 Functional Block Diagram
82P33741 Functional Block Diagram
  • Supports 3 independent timing paths: IEEE 1588, physical layer (SyncE, SONET/SDH, PDH, CPRI/OBSAI) and recovered line clock
  • Phase synchronizes IEEE 1588 TSUs (Time Stamp Units) at network ports with redundant system-wide IEEE 1588 clock and sync pulse pairs: 1PPS (Pulse Per Second) sync pulses
  • Precise 1PPS edge alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • Frequency synchronizes physical layer ports with redundant system-wide frequency references
  • Generates clocks for: 10GBASE-R, 10GBASE-W, 40GBASE-R and CPRI/OBSAI interfaces without external jitter attenuators: jitter generation <0.3 ps RMS (10 kHz to 20 MHz)
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Prevents time errors and PHY bit errors with automatic reference switching, optional hitless reference switching and revertive or non-revertive reference switching
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 144 pin CABGA package

Documentation

Title Type Date
82P33741 Datasheet
PDF916 KB
Datasheet
IDT Products for Wired Broadband Applications
PDF686 KB
Application Brief
AN-827 Application Relevance of Clock Jitter
PDF1.99 MB
Application Note
AN-807 Recommended Crystal Oscillators for Network Synchronization
PDF148 KB
Application Note
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment
PDF324 KB
Application Note
AN-861 Recommended Crystals for IDT VCXO-based Synchronization PLLs
PDF300 KB
Application Note
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx
PDF249 KB
Application Note
AN-828 Termination - LVPECL
PDF322 KB
Application Note
AN-844 Termination - AC Coupling Clock Receivers
PDF170 KB
Application Note
AN-845 Termination - LVCMOS
PDF146 KB
Application Note
AN-846 Termination - LVDS
PDF133 KB
Application Note
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
Application Note
AN-840 Jitter Specifications for Timing Signals
PDF442 KB
Application Note
AN-838 Peak-to-Peak Jitter Calculations
PDF115 KB
Application Note
AN-839 RMS Phase Jitter
PDF233 KB
Application Note
AN-835 Differential Input with VCMR being VIH Referenced
PDF160 KB
Application Note
AN-836 Differential Input to Accept Single-ended Levels
PDF120 KB
Application Note
AN-815 Understanding Jitter Units
PDF565 KB
Application Note
AN-801 Crystal-High Drive Level
PDF202 KB
Application Note
AN-805 Recommended Ferrite Beads
PDF121 KB
Application Note
AN-806 Power Supply Noise Rejection
PDF438 KB
Application Note
Timing Fabric for Next Generation Communications Equipment Overview
PDF1.31 MB
Overview
IDT Clock Generation Overview
PDF1.83 MB
Overview
Timing Fabric for Communications Equipment Overview
PDF263 KB
Overview
PCN# : A1702-01 Changed Mold Compound and Solder Paste on Select Packages
PDF93 KB
Product Change Notice
ITU-T Profiles for IEEE 1588
PDF1.17 MB
White Paper
info: For device-specific or order-specific documentation, submit a support request.

Design & Development

Boards & Kits

82EBP33831 Evaluation Board - top view

82EBP33831

Evaluation
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Evaluation Board for 82P33831 Synchronization Management Unit for IEEE 1588 and 10G/40G Synchronous Ethernet

The 82EBP33831 Evaluation board for IEEE 1588 and Synchronous Ethernet allows the user to connect up to eight differential ended, up to eight single ended, and up to two Composite (AMI) reference inputs via SMA connectors. The inputs can operate at any frequency from 1PPS to 650MHz.
Featured Documents:
82EBP33831 Evaluation Board User Guide

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IDT Releases World’s First IEEE 1588 Time and Frequency Generators Transparently Disciplined by Synchronous Ethernet News