The 82P33741 Port Synchronizer for IEEE 1588 and 10G/40G Synchronous Ethernet provides tools to manage timing references, clock conversion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock generation; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize 40GBASE-R, 10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper
Features
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Supports 3 independent timing paths: IEEE 1588, physical layer (SyncE, SONET/SDH, PDH, CPRI/OBSAI) and recovered line clock
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Phase synchronizes IEEE 1588 TSUs (Time Stamp Units) at network ports with redundant system-wide IEEE 1588 clock and sync pulse pairs: 1PPS (Pulse Per Second) sync pulses
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Precise 1PPS edge alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
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Frequency synchronizes physical layer ports with redundant system-wide frequency references
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Generates clocks for: 10GBASE-R, 10GBASE-W, 40GBASE-R and CPRI/OBSAI interfaces without external jitter attenuators: jitter generation <0.3 ps RMS (10 kHz to 20 MHz)
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Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
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Prevents time errors and PHY bit errors with automatic reference switching, optional hitless reference switching and revertive or non-revertive reference switching
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DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
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Automatically loads configuration from an external EPROM after reset without processor intervention
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144 pin CABGA package