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Features

  • Input offset voltage: ±3 mV MAX.
  • Slew rate: 5.5 V/μ s TYP.
  • Unity gain frequency: 2.8 MHz TYP.
  • Low power: ICC ≤ 2.2 mA MAX. (Reduces circuit currents while maintaining relatively high slew rate and bandwidth)
  • High stability is secured to capacitive loads (4000 pF, AV = +1)
  • Internal frequency compensation
  • Small package The whole size of the package is downsized by 30 to 40% compared with a standard SOP contour, by using a TSSOP (3 x 3 mm² body) package

Description

The μ PC835 is the higher version of μPC832 and 4062, the J-FET input operational amplifiers, in stability and accuracy. The μ PC835 is a J-FET input dual operational amplifier which realizes both low power consumption and high stability, by adopting a High-Speed PNP transistor of fT = 300 MHz on its output stage. In addition, despite its J-FET input, the μ PC835 realizes low offset voltage characteristics that eclipses conventional general operational amplifiers, by using a resistance trimming system, the proven method for our high accuracy operational amplifier and high accuracy reference voltage. The μ PC835 is ideal for use in measurement instruments and control instruments, which especially requires the stability during capacitive load connections.

Parameters

Attributes Value
Channels (#) 2
Temp. Range (°C) -40 to +85
Bandwidth (MHz) 2.8
Offset Voltage (Max) (mV) 3
IBIAS (nA) 0.05
CMRR (dB) 80
Rail-to-Rail Input No
Rail-to-Rail Output No
Common Mode Input Voltage Range (V) 5 - 16
Output Voltage Swing Range (V) V-+3 - V+-3
IS per Amp (mA) 1.4
Single Supply Voltage Range (V) -
Slew Rate (V/µs) 5.5
VS (Min) (V) 5
VS (Max) (V) 16
Topology [Rail 1] -
Enable -
Input Offset Voltage Vio (Max) (mV (±)) 3
Supply Current Icc/Idd (Max) (mA) 2.2
Qualification Level Standard
Simulation Model Available SPICE

Package Options

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
TSSOP 3 x 3 x 1.1 8 0.65

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