Ian Dobson
Timing Products Marketing Director
Published: March 22, 2019

Whether it’s streaming audio or video content, posting to video apps like Instagram or immersing ourselves in online worlds with games like Fortnite, we all want lots of bandwidth. And it better be low latency. There will be heck to pay if my game character dies due to a lagging connection or I have to wait to see who got voted off the island on Housewife Survivor season 45.

Delivering on that desire requires upgrades not only in the wireless networks we all hear about, but also those that support both mobility and fixed-location use.

Wired networks are moving to optical connections with higher data rates. In some cases that just means a fast rate on the fiber. In other cases, it means going to multi-level encodings like PAM4 to deliver more data at the same symbol rate. In both cases, this means lower phase noise reference clocks to the physical layer (PHY) chips on boards or within fiber-optic modules.  

Those reference clocks are also increasing in frequency. It used to be that the PHYs were content to multiply-up the clock frequency internally. However, physics interfered, as it often does. Every doubling of frequency will worsen the phase noise by 6dB. The PHY vendors react to this by removing the need to multiply inside their chips and pushing this off onto the timing silicon vendors like Renesas. Despite what we say around the water cooler at Renesas, this is not done out of spite. PHYs are often built in low-geometry silicon processes that excel at implementing complex digital logic, but are not nearly as good for implementing the types of analog circuits needed to generate low-noise clocks.

Using a crystal oscillator (XO) to generate those reference clocks was the go-to choice in the past, but fewer XO vendors are able to support the phase noise targets and especially the higher frequencies required by more recent PHY devices. Those few that can will want premium prices.

Increasingly, PHY reference designs are turning to silicon timing vendors like Renesas to provide these clocks on the PHY reference design boards. Devices like Renesas' ClockMatrix™ family of multi-channel timing solutions provide the low phase noise, higher frequencies and frequency-plan flexibility needed for the latest generations of PHY devices. Renesas is an ideal partner for many of the PHY vendors since Renesas does not have its own line of competitive PHYs.

More bandwidth will solve part of the latency concern by ensuring your data is not queued behind someone else’s in a router or datacenter somewhere in the cloud. However, that’s only part of the solution. Moving the source of the data closer to the users is another part. This means those functions that were once housed in nice, comfy, climate-controlled data centers or switching offices are now in green boxes on people’s lawns, in underground cabling bays or mounted on poles and subject to the vagaries of Mother Nature. The silicon servicing these applications not only has to operate from -40°C to +85°C, it has to operate without airflow. Systems in these distributed locations can’t have fans drawing in the air since that requires filters which would need periodic cleaning, adding to operational costs.

Renesas' ClockMatrix family not only supports that wide temperature range, but it also has low-power consumption on a per-channel basis and supports QFN packaging that allows efficient conduction cooling.

For more details on the ClockMatrix family of solutions, including technical documentation and samples, check out

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