The 8530F-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the 8530F-01 ideal for those clock distribution applications demanding well defined performance and repeatability.

Features

  • Sixteen differential LVPECL output pairs
  • CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input
  • Output skew: 20ps (typical)
  • Additive phase jitter, RMS @ 106.25MHz: 0.11ps (typical)
  • Full 3.3V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

tuneProduct Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TQFP 48 C Yes Tray
Availability
Obsolete TQFP 48 C Yes Reel
Availability

descriptionDocumentation

Title language Type Format File Size Date
Datasheets & Errata
star 8530-01 Data Sheet Datasheet PDF 246 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Other
Clock Distribution Overview Overview PDF 217 KB
IDT Clock Generation Overview Overview PDF 1.83 MB

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