Overview
Description
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
Features
- Low skew, low jitter PLL clock driver
- Max frequency supported = 400MHz (DDRII 800)
- I2C for functional and output control
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Programmable skew through SMBus
- Frequency defect control through SMBus
- Individual output control programmable through SMBus
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Product Options
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