Overview
Description
The Intersil HCTS540MS is a radiation hardened inverting octal buffer/line driver, with two active-low output enables. The output enable pins (OE1 and OE2) control the three-state outputs. If either enable is high, the outputs will be the high impedance state. For data output, both enables (OE1 and OE2) must be low. The HCTS540MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS logic family. The HCTS540MS is supplied in a 20-lead ceramic flatpack (K suffix) or an SBDIP package (D suffix).
Features
- 3 micron radiation hardened CMOS SOS
- Total dose 200K RAD (Si)
- SEP effective LET no upsets: >100 MEV-cm2/mg
- Single Event Upset (SEU) immunity <2 x 10-9 errors/ bit-day (Typ)
- Dose rate survivability: >1 x 1012 RAD (Si)/s
- Dose rate upset >1010 RAD (Si)/s 20ns pulse
- Latch-up free under any conditions
- Fanout (over temperature range)
- Bus driver outputs 15 LSTTL loads
- Military temperature range: -55 °C to +125 °C
- Significant power reduction compared to LSTTL ICs
- DC operating voltage range: 4.5V to 5.5V
- LSTTL input compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
- Input current levels Ii ≤5µA at VOL, VOH
Comparison
Applications
Documentation
Featured Documentation
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| Type | Title | Date |
| Datasheet | PDF 413 KB | |
| Brochure | PDF 5.02 MB | |
| Brochure | PDF 467 KB | |
| Price Increase Notice | PDF 360 KB | |
| Other | ||
| White Paper | PDF 533 KB | |
| Product Advisory | PDF 499 KB | |
| Product Change Notice | PDF 230 KB | |
| Application Note | PDF 224 KB | |
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Design & Development
Models
ECAD Models
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