Overview
Description
The 71V256SA 3.3V CMOS Asynchronous SRAM is organized as 32K x 8. When in standby mode, its very low power characteristics contribute to extended battery life. Under full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to be less than 6.6mW. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
Features
- Ideal for high-performance processor secondary cache
- Commercial (0C to +70C) and Industrial (–40C to +85C) temperature range options
- Fast access times: – Commercial and Industrial: 10/12/15/20ns
- Low standby current (maximum): – 2mA full standby
- Inputs and outputs are LVTTL-compatible
- Single 3.3V(±0.3V) power supply
- Available in 28-pin SOJ and 28-pin TSOP type I packages
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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