Features
- Twenty-four LVCMOS outputs, 7Ω typical output impedance
- Selectable differential clock input pairs for redundant clock applications
- CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
- Maximum output frequency: 167MHz
- Translates any differential input signal (LVPECL, LVHSTL, LVDS) to LVCMOS without external bias networks
- Translates any single-ended input signal to LVCMOS with resistor bias on nCLK input
- Multiple output enable pins for disabling unused outputs in reduced fanout applications
- Output skew: 275ps (maximum)
- Part-to-part skew: 600ps (maximum)
- Bank skew: 150ps (maximum)
- Propagation Delay: 4.3ns (maximum)
- 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
Description
The 8344 is a low voltage, low skew, 1-to-24 Differential-to-LVCMOS Fanout Buffer. The 8344 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. 8344 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 8344 ideal for those clock distribution applications demanding well defined performance and repeatability.
Support Communities
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R_RIIC_MasterRead not blocking?
With SSP 1.1.3 I'm using the r_riic driver to access an MPU9250 motion sensor. I2c speed is 400. As with most I2C devices with internal registers, reading a register works as follows: i2c write with start to the slave address and provide a register address i2c ...
May 31, 2017 -
Sleep Mode Power Too High - 14586 design migrated from da14583
hi, i ma moving a design from the da14583 to the da14586 and cannot achive the same sleep mode current measurements. i have the same PCB layout. the design supports an LCD whose enable pin is set on Port 2_3, which is also used by as SPI_EN_GPIO ...
Sep 12, 2019 -
J-Link Firmware update filed
Hello! I am using DA14580DEVKT-B. I got a popup about updating J-LINK in Keil v5, and I clicked OK. After that, I got a window with the following contents: SEGGER J-Link V6.52e Firmware Update New firmware: J-Link OB-SAM3U128V1 compiled Aug 22 2019 17:29 ...
Oct 18, 2019
Support Communities
