Overview
Description
The 9FGV0841 is an 8-output very low power clock generator for PCIe Gen1–4 applications with integrated output terminations providing Zo=100 Ω. The device has 8 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.
For information regarding evaluation boards and material, please contact your local IDT sales representative.
Features
- PCIe Gen1–4 compliant
- Integrated terminations provide 100Ω differential Zo: reduced component count and board space
- 1.8V operation: reduced power consumption
- Outputs can optionally be supplied from any voltage between 1.05V and 1.8V: maximum power savings
- OE# pins: support DIF power management
- LP-HCSL differential clock outputs: reduced power and board space
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- DIF outputs blocked until PLL is locked: clean system start-up
- Selectable 0%, -0.25% or -0.5% spread on DIF outputs: reduces EMI
- External 25MHz crystal; supports tight ppm with 0ppm synthesis error
- Configuration can be accomplished with strapping pins: SMBus interface not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 6 × 6 mm 48-VFQFPN; minimal board space
- Selectable SMBus addresses: multiple devices can easily share an SMBus segment
- Available in AEC-Q100 qualified, Grade 2 (-40°C to +105°C) version (wettable flank package)
Comparison
Applications
Design & Development
Software & Tools
Boards & Kits
Evaluation
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Test this Board Remotely
Available on Lab on the Cloud, use our PC-based GUI to instantly start configuring and testing designs in our virtual lab, no physical board needed.
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Product Options
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Videos & Training
PCIe Reference Clock Jitter Budgets
Ron Wade, chief PCIe system architect explains the fundamental difference in reference clock jitter budgets between the first three generations of the specification and those of Gen4 and Gen5 which raise new challenges for designers.
Related Resources
Video List
News & Blog Posts
Blog Post
Apr 14, 2022
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Blog Post
Feb 7, 2019
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Blog Post
May 22, 2018
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News
Apr 30, 2018
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