Package Information
| Lead Count (#) | 40 |
| Pkg. Code | NLG40 |
| Pitch (mm) | 0.5 |
| Pkg. Type | VFQFPN |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.9 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
Product Attributes
| Lead Count (#) | 40 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 5000 |
| Qty. per Carrier (#) | 0 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Additive Phase Jitter Typ RMS (fs) | 65 |
| Additive Phase Jitter Typ RMS (ps) | 0.065 |
| Adjustable Phase | No |
| Channels (#) | 1 |
| Core Voltage (V) | 2.5 |
| Family Name | 8SLVD |
| Function | Buffer, Multiplexer |
| Input Freq (MHz) | 0 - 2000 |
| Input Type | LVPECL, LVDS, CML |
| Inputs (#) | 2 |
| Length (mm) | 6 |
| Longevity | 2040 Apr |
| MOQ | 5000 |
| Noise Floor (dBc/Hz) | -160 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 0 - 2000 |
| Output Skew (ps) | 45 |
| Output Type | LVDS |
| Output Voltage (V) | 2.5 |
| Outputs (#) | 12 |
| Package Area (mm²) | 36.0 |
| Pitch (mm) | 0.5 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.9 |
| Pkg. Type | VFQFPN |
| Reel Size (in) | 13 |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Supply Voltage (V) | 2.5 - 2.5 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.9 |
| Width (mm) | 6 |
Description
The 8SLVD1212 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase noise clock and data signals. The 8SLVD1212 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1212 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.