Package Information
| Lead Count (#) | 32 |
| Pkg. Code | PRG32 |
| Pitch (mm) | 0.8 |
| Pkg. Type | TQFP |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
Product Attributes
| Lead Count (#) | 32 |
| Carrier Type | Tray |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 0 |
| Qty. per Carrier (#) | 250 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Advanced Features | Feedback Input |
| C-C Jitter Max P-P (ps) | 45 |
| Core Voltage (V) | 2.5, 3.3 |
| Feedback Input | Yes |
| Input Freq (MHz) | 15.625 - 250 |
| Input Type | HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL |
| Inputs (#) | 2 |
| Length (mm) | 7 |
| MOQ | 2000 |
| Output Banks (#) | 1 |
| Output Freq Range (MHz) | 15.625 - 250 |
| Output Skew (ps) | 55 |
| Output Type | LVCMOS |
| Output Voltage (V) | 2.5, 3.3 |
| Outputs (#) | 8 |
| Package Area (mm²) | 49.0 |
| Phase Jitter Max RMS (ps) | 50.000 |
| Pitch (mm) | 0.8 |
| Pkg. Dimensions (mm) | 7.0 x 7.0 x 1.4 |
| Pkg. Type | TQFP |
| Prog. Clock | No |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Tape & Reel | No |
| Thickness (mm) | 1.4 |
| Width (mm) | 7 |
Description
The 8705I is a highly versatile 1:8 Differential-to- LVCMOS/LVTTL Clock Generator. The 8705I has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels. The 8705I has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.