Overview
Description
Dual DDR zero delay buffer
Features
- High performance, low jitter zero delay buffer
- I2C for functional and output control
- Dual bank 1-6 differential clock distribution
- 2 separate feedback in & out for input to output
- Synchronization for each bank
- Supports up to 4 DDR DIMMs
- Supports up to 533MHz (DDRII 1066)
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
Product Options
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