Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.


  • 14-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • 50% more dynamic driver strength than standard SSTU32864
  • Supports LVCMOS switching levels on C1 and RESET# inputs
  • Low voltage operation


タイトル language 分類 形式 サイズ 日付
star 74SSTUBF32869A Datasheet データシート PDF 493 KB
PCN#: A1309-03 Additional Assembly Sources 製品変更通知 PDF 398 KB
PDN# : CQ-20-05 End-of-Life (EOL) Process on Select Part Numbers 製品中止通知 PDF 720 KB