CK440Q Lite PCIe Gen6 Server Clock Generator
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Overview
Description
The 9SQ445 is a CK440Q Lite clock synthesizer for newer Intel-based server platforms. The 9SQ445 is a single-chip, PCIe Gen6 compliant device. It is designed to work as a complete clock solution, or in combination, with DB2000Q-compliant or other clock buffers to provide point-to-point clocks to multiple receiving agents.
Features
- PCIe Gen5 phase jitter < 50fs rms
- PCIe Gen6 phase jitter < 40fs rms
- 3.3V operation
- Three 100MHz dedicated output pairs with individual OE# pins
- Two MXCLK output pairs multiplexable between 100MHz and 25MHz
- One 25MHz dedicated output pair
- 85Ω differential Low-Power HCSL (LP-HCSL) outputs eliminate 24 resistors, saving 39mm2 of area
- Three selectable SMBus addresses
- Supports 0%, -0.3% and -0.5% spread-spectrum amounts
- Side-Band Interface allows real-time hardware control of all output enables
- 5 × 5 mm, 40-VFQFPN
- -40°C to +85°C operating temperature range
Documentation
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Overview
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Overview
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White Paper
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Product Options
Processing table
| VFQFPN | 40 | -40 to 85°C | 85 | Yes | Tray | Get Samples, | |
| VFQFPN | 40 | -40 to 85°C | 85 | Yes | Reel |
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play_circle_filledVideos & Training
Comparing PCI Express® Gen 3-6 Jitter Filters to a 12k-20M Jitter Filter
This video provides a brief comparison of PCIe Gen3-6 common clock jitter filters vs. a typical 12k to 20MHz jitter filter plot. The tutorial explains what noise frequencies PCIe Gen6 is most sensitive to, and why it's important to minimize jitter in the 1MHz to 50MHz region. Presented by Ron Wade, system architect at Renesas. For more information about Renesas’ PCIe timing solutions, visit renesas.com/pcietiming
Video List
