An overview of IDT's full-featured PCI Express (PCIe) clock zero-delay buffers and fanout buffers addressing PCIe Gen 1, Gen 2, Gen 3, and Gen 4.
Presented by Ron Wade, System Architect at IDT. For more information about IDT's PCIe zero-delay buffers and PCIe fanout buffers, visit http://www.idt.com/products/clocks-timing/application-specific-clocks/pci-express-clocks/pci-express-clock-buffers-and-multiplexers.
Hi there, this is Ron Wade with IDT. Welcome back to the third part of a five-part series on full-featured PCIe clocks. This part of the series covers zero-delay and fanout buffers. So focusing slightly on the 3.3-volt members of the family because those are the newest, we have zero delay buffers that range from two outputs up to eight outputs. These devices are gen 1 through 4 common clock compliant as well as gen 2 and 3 SRIS compliant. We offer parts with both 100-ohm and 85-ohm outputs so you can work in either industry standard or Intel server environments with no external termination components. Very important here also is the pin control of the PLL bandwidth, high or low, as well as PLL bypass mode.
The devices are offered in package sizes ranging from 4x4 to 6x6 millimeter QFN and with the DBL parts which are the 3.3-volt parts, we do have the ability to customize these parts via OTP at the factory for you. I'd like to emphasize that the standard parts are available off the shelf with no programming required, but we do have the ability to customize for you. For instance, you might want to have a different slew rate, you might want to change the default output amplitude, you may wish to have an output enabled pin with an active high polarity instead of an active low polarity. Well, we're able to do all of this at the factory very quickly and very easily.
The other thing I’d like to mention is that the 3.3-volt 9DBL parts are members of the full-featured PCIe zero-delay family which includes the 1.5 and 1.8-volt parts that have been in the market for a while. I’d like to just briefly review the key features here. We're meeting all of the upcoming phase jitter requirements for PCIe reference clocks today so that you can design your design today with these parts and then amortize that design over a couple of generations of devices.
The maximum power consumption of the DBL devices is a little bit over 211 milliwatts. That's the typical value at 3.3 volts which is a significant power savings over our legacy parts. This reduces heat dissipation and it also helps you meet EPA Energy Star requirements if that is something that your design is subject to. The integrated terminations are great because not only do they save you up to 32 resistors off of your BOM, they also save you up to 55 square millimeters of package area.
So the 9DBL parts are the newest member of our full-featured PCIe zero-delay buffer family which includes the 9DBV parts at 1.8 volts and the 9DBU parts at 1.5 volts. Again, the 3.3-volt parts are gen 1 through 4 and support the common clock, the SRnS and the SRIS clocking architectures. We're investigating these newer standards for the 1.5 and 1.8-volt parts, basically evaluating our characterization data to see how it stacks up and that process is ongoing. As far as pin compatibility goes, at the six and the eight output levels, you have pin compatibility across all three power supply voltages. And at the two and four output levels, the 1.5 and 1.8-volt parts share pin compatibility, the 3.3 volt part is slightly different.
So let's switch gears for a second to the fanout buffers. These are simpler than the ZDBs because they have no PLL inside. That means that they do have about 50 milliwatts or 40 milliwatts less power consumption and they support all of the upcoming PCI Express reference clock requirements for gen 4 and gen 2 and 3 SRIS. Again, the same 100-ohm and 85-ohm offerings in the family. These are pin compatible with the ZDBs. So, the 9DBL04 part is pin compatible with the 9DBL05, the 9DBL06 is pin compatible with the 9DBL07 and the 9DBL08 ZDB is pin compatible with a 9DBL09 fanout buffer.
These parts are available 5x5 to 6x6 millimeter QFN packages. OTP customization is available with the DBLs in the 3.3-volt family. And again, we have 1.5 and 1.8-volt versions of these devices available if, for instance, you need to emphasize additional power savings. So supporting all of the upcoming standards today means that you can again amortize your design over several generations of product, lowering your development costs. The 177 milliwatts cuts the power consumption greatly compared to legacy devices and also greatly aids in meeting EPA Energy Star requirements if that is something that your design is subject to. The integrated terminations with the fan-out buffers save up to 36 resistors eliminating them from your BOM as well as saving over 67 mm2 of board area.
So the full-featured PCIe fanout buffer family, again, we've got the 3.3-volt devices, the 9DBLs, the 9DBVs at 1.8, the 9DBUs at 1.5. And the DBLs being the newest, support the newest upcoming standards. We're evaluating the 1.5 and 1.8 to see what we can do with those to bring them into the newer generation performance requirements. Pin compatibility on the fanout buffers across all three operating voltage devices is seven and nine outputs and then pin compatibility at five outputs is limited to the 1.5 and 1.8-volt parts because the 3.3-volt part has a slightly different footprint.
Okay, so why would you use an eight-output 9DBL part instead of a 9DB108, 9DB833 device? Well, the main reason is performance. The performance standards are listed in the middle of the spec limit category here and then the actual performance of the various devices is listed under their column heading. So the DBL08 is on the right, it is the 3.3-volt ZDB. And it shows a little bit better improvement on the gen 1 peak-to-peak jitter but on gen two low-band and on gen three and four, it is significantly lower jitter than even the 9DB833 device which is the gen three part. The 9DB803 is only a gen two device. The 9DB108 mentioned at the top was only a gen one device and is not listed on this table. So the other thing that's in the 9DBL08 data sheet is 12k-20M additive phase jitter spec in fan-out buffer mode. And you won't find that on the older current mode legacy parts.
The big savings comes--besides the better performance--the big savings comes in reduced board area. You're going from over 100 mm2 down to 36 mm2. You're saving 32 resistors on your BOM and your typical power, even if you're using only 3.3 volts, is one-third of the legacy parts. If you care to power your outputs from 1.05 volts, you can actually reduce your power even further down to as low as 130 milliwatts. So why use the DBL08? Well, it's up to 70% less phase jitter, 64% less area, over 80% less power, 32 resistors taken off the BOM, and if you will need even more power savings, you can use the 1.8 volt or the 1.5-volt parts. Thank you for watching and stay tuned for the other parts in the series.