The 71V2556 3.3V CMOS Synchronous SRAM is organized as 128K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V2556 contains data I/O, address and control signal registers. It can provide four cycles of data for a single address presented to the SRAM.


  • High performance system speed 166 MHz (3.5 ns Clock-to-Data Access)
  • ZBTTM Feature - No dead cycles between write and read cycles
  • Internally synchronized output buffer enable eliminates the need to control OE
  • Single R/W (READ/WRITE) control pin
  • Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications
  • 4-word burst capability (interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • 3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
  • Optional - Boundary Scan JTAG Interface (IEEE 1149.1 complaint)
  • Available in 100-pin TQFP and 119-pin BGA packages




Design & Development