Overview
Description
The 8T39S11A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to ten differential outputs which can be configured as LVPECL, LVDS, or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.
Features
- Two differential reference clock input pairs
- Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL, HSTL, or single-ended
- Crystal input accepts 10MHz to 40MHz crystal or single-ended clock
- Maximum output frequency
LVPECL - 2GHz
LVDS - 2GHz
HCSL - 250MHz
LVCMOS - 250MHz - Two banks, each has five differential output pairs that can be configured as LVPECL, LVDS, or HCSL
- One single-ended reference output with synchronous enable to avoid clock glitch
- Output skew: 80ps (maximum)
(Bank A and Bank B at the same output level) - Part-to-part skew: 200ps (typical)
- Additive RMS phase jitter at 156.25MHz:
5.6fs RMS (10kHz to 1MHz), typical at 3.3V/3.3V
34.7fs RMS (12kHz to 20MHz), typical at 3.3V/3.3V - Supply voltage modes:
VDD/VDDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V - -40 °C to 85 °C ambient operating temperature
- Lead-free (RoHS 6) packaging
Comparison
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Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
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| Buff Up Your Design with Renesas Clock Buffers | Blog Post | Dec 15, 2018 |