The 553S is a low skew, single input to four output, LVCMOS clock buffer. The 553S has best in class additive phase Jitter of sub 50 fsec.


  • Low additive phase jitter RMS: 50fs
  • Extremely low skew outputs (50ps)
  • Low cost clock buffer
  • Packaged in 8-pin SOIC and small 8-pin DFN packages, Pb-free
  • Input / Output clock frequency up to 200MHz
  • Ideal for networking clocks
  • Operating voltages: 1.8V to 3.3V
  • Output Enable mode tri-states outputs
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)


Document title Document type
Date Date
PDF 313 KB Datasheet
PDF 146 KB Application Note
PDF 495 KB Application Note
PDF 442 KB Application Note
PDF 565 KB Application Note
PDF 217 KB Overview
PDF 1.83 MB Overview
PDF 268 KB Product Change Notice
PDF 611 KB Product Change Notice
PDF 611 KB Product Change Notice
10 items

Design & Development



Title Type Type Date Date
ZIP 26 KB Model - IBIS
1 item


Low-jitter LVCMOS Fanout Clock Buffers by IDT