NOTICE - The following device(s) are recommended alternatives:

The 9ZXL0851 is a low-power 8-output differential buffer that meets all the performance requirements of the Intel DB1200ZL specification. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.

Features

  • 8 – 0.7V low-power HCSL-compatible output pairs
  • LP-HCSL outputs with Zo = 85ohms ; save power and board space - no termination resistors required.
  • Space-saving 48-pin VFQFPN package 
  • Fixed feedback path for 0ps input-to-output delay
  • 8 OE# pins; hardware control of each output
  • PLL or bypass mode; PLL can dejitter incoming clock
  • 100MHz or 133MHz PLL mode operation; supports PCIe and QPI applications
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's
  • Spread Spectrum Compatible; tracks spreading input clock for low EMI
  • Cycle-to-cycle jitter < 50ps 
  • Output-to-output skew < 65 ps
  • Input-to-output delay variation < 50ps
  • PCIe Gen3 phase jitter < 1.0ps RMS
  • QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
9ZXL0851AKLF
Active VFQFPN 48 C Yes Tray
Availability
9ZXL0851AKLFT
Active VFQFPN 48 C Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
9ZXL0851A Datasheet Datasheet PDF 328 KB
Application Notes & White Papers
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-808 PCI Express/HCSL Termination Application Note PDF 137 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Other
PCI Express Timing Solutions Overview Overview PDF 275 KB
9ZXL0851 Reference Schematic Schematic PDF 17 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB