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The ClockMatrix family of devices are high-performance, precision timing solutions designed to simplify clock designs for applications with up to 800Gbps interface speeds.
They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation, and phase alignment. The device can be used to precisely synchronize IEEE 1588 Time Stamp Units (TSUs) and SyncE ports on wireless baseband, DU, CU, RU, fronthaul or backhaul networks. The family of devices support multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generation including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 112Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC, and IEEE 1588 TSUs. To easily implement synchronization in IEEE 1588 systems, Renesas offers PTP clock manager software for free under license.
Key features include:
- Flexibility – PLL channels are individually configurable as a synthesizer, jitter attenuator, or DCO
- Integration – up to 8 DPLLs and 14 outputs in a single package
- Performance – RMS jitter as low as 88 fs (typ)
- Standards compliant – IEEE 1588, OTN, and SyncE
- Programmable – I2C, SPI or OTP
- Device Monitoring – Built-in ability to monitor reference inputs, DPLL and APLL loss of lock, Holdover status
- Right size for the job – Package options from 144-BGA down to 48-QFN
Featured Document: ClockMatrix Family Overview
