概要

説明

The 71V546 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V546 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.

特長

  • Supports high performance system speed - 133 MHz
  • (4.2 ns Clock-to-Data Access)
  • ZBTTM Feature - No dead cycles between write and read
  • cycles
  • Internally synchronized registered outputs eliminate the
  • need to control OE
  • Single R/W (READ/WRITE) control pin
  • Positive clock-edge triggered address, data, and control
  • signal registers for fully pipelined applications
  • 4-word burst capability (interleaved or linear)
  • Individual byte write (BW1 - BW4) control (May tie active)
  • Three chip enables for simple depth expansion
  • Single 3.3V power supply (±5%)
  • Available in 100-pin TQFP package

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