Crystal or Differential to Differential Clock Fanout Buffer
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概要
Description
The 8T39210 is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to ten differential outputs that can be configured as LVPECL, LVDS, or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V
or 2.5V output operating supply.
特長
- Two differential reference clock input pairs
- Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL, HSTL, or single-ended
- Crystal Input accepts 10MHz to 40MHz Crystal or single-ended clock
- Maximum Output Frequency:
- LVPECL – 1.5GHz
- LVDS – 1.5GHz
- HCSL – 250MHz
- LVCMOS – 250MHz
- Two banks, each has five differential output pairs that can be configured as LVPECL, LVDS, or HCSL
- One single-ended reference output with synchronous enable to avoid clock glitch
- Output skew: 81ps (maximum), Bank A and Bank B at the same output level
- Part-to-part skew: 200ps (typical)
- Additive RMS phase jitter at 156.25MHz: 37.6fs RMS (12kHz–20MHz), typical at 3.3V/3.3V
- Supply voltage modes:
- VDD/VDDO
- 3.3V/3.3V
- 3.3V/2.5V
- 2.5V/2.5V
- -40°C to 85°C ambient operating temperature
- 7 × 7 mm 48-VFQFPN lead-free (RoHS 6) packaging
ドキュメント
| タイトル | 分類 | 日付 降順で並び替え | |
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データシート
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概要
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PDF550 KB
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製品変更通知
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設計・開発
モデル
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製品選択
Processing table
| VFQFPN | 48 | I | Yes | Tray | サンプルを入手, | |
| VFQFPN | 48 | I | Yes | Reel |
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ニュース＆ブログ
| Buff Up Your Design with Renesas Clock Buffers | ブログ | 2018年12月15日 |
