The 8SLVP1212I is a high-performance, 12 output differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1212I is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1212I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and twelve low skew outputs are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Twelve low skew, low additive jitter LVPECL outputs
  • Two selectable, differential clock inputs
  • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 2GHz
  • LVCMOS interface levels for the control input (input select)
  • Output skew: 15ps (typical)
  • Propagation delay: 550ps (maximum)
  • Low additive phase jitter, RMS: <50fs (typical)
  • Full 3.3V and 2.5V supply voltage
  • Device current consumption (IEE): 118mA (typical)
  • Available in Lead-free (RoHS 6), 40-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

tuneProduct Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active VFQFPN 40 I Yes Tray
Availability
Active VFQFPN 40 I Yes Reel
Availability
Active VFQFPN 40 I Yes Reel
Availability

descriptionDocumentation

Title language Type Format File Size Date
Datasheets & Errata
star 8SLVP1212 Datasheet Datasheet PDF 737 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : TB1311-01 New Carrier Tape on VFQFPN-28, VFQFPN-40, VFQFPN-48 Product Change Notice PDF 790 KB
Other
RF Timing Family Product Overview Overview PDF 331 KB
Clock Distribution Overview 日本語 Overview PDF 217 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB

file_downloadDownloads

Title language Type Format File Size Date
Models
8SLVP1212I IBIS Model Model - IBIS ZIP 72 KB

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