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621

Obsolete

Low Skew 1 to 4 Clock Buffer

621 Datasheet
NOTICE - The following device(s) are recommended alternatives:
621S - Low Skew 1 to 4 Clock Buffer

Overview

The 621 is a low skew, single input to four output, clock buffer. The device operates from a single 1.2 to 1.8 volt supply and has a 3.3 volt tolerant input, making it ideal for level translation. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.

621 - Block Diagram
621 - Pinout
621 - Block Diagram
621 - Pinout
  • Low skew outputs (150 ps)
  • Packaged in 8-pin SOIC or 8-pin DFN (2x2mm)
  • RoHS 5 or RoHS 6 (lead-free) package
  • Low power CMOS technology
  • Operating voltages of 1.2 V to 1.8 V
  • Output Enable pin tri-states outputs
  • 3.3 V tolerant input clock
  • Industrial or commercial temperature ranges

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

Explore ECAD Models
Diagram of ECAD Models

Models
Type Title Date
Model - IBIS
ICS621_1p8 IBIS Model
ZIP 7 KB
1 item

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