Package Information
| Pitch (mm) | 0.65 |
| Lead Count (#) | 28 |
| Pkg. Type | VFQFPN |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.85 |
| Pkg. Code | NLG28 |
Environmental & Export Classifications
| Moisture Sensitivity Level (MSL) | 3 |
| Pb (Lead) Free | Yes |
| ECCN (US) | NLR |
| HTS (US) | 8542390001 |
Product Attributes
| Pkg. Type | VFQFPN |
| Lead Count (#) | 28 |
| Carrier Type | Reel |
| Moisture Sensitivity Level (MSL) | 3 |
| Qty. per Reel (#) | 5000 |
| Qty. per Carrier (#) | 0 |
| Package Area (mm²) | 36.0 |
| Pitch (mm) | 0.65 |
| Pkg. Dimensions (mm) | 6.0 x 6.0 x 0.85 |
| Pb (Lead) Free | Yes |
| Pb Free Category | e3 Sn |
| Temp. Range | -40 to +85°C |
| Accepts Spread Spec Input | Yes |
| Advanced Features | Accepts Spread Spec Input, Spread Spectrum, Reference Output |
| Core Voltage (V) | 3.3 |
| Die Form | No |
| Input Freq (MHz) | 1 - 400 |
| Input Type | Crystal, LVCMOS |
| Inputs (#) | 1 |
| Length (mm) | 6 |
| MOQ | 5000 |
| Output Banks (#) | 6 |
| Output Freq Range (MHz) | 0 - 500 |
| Output Skew (ps) | 150 |
| Output Type | LVCMOS, LVPECL, LVDS, HCSL |
| Output Voltage (V) | 3.3 |
| Outputs (#) | 8 |
| Period Jitter Max P-P (ps) | 200.000 |
| Period Jitter Typ P-P (ps) | 150.000 |
| Prog. Clock | Yes |
| Prog. Interface | I2C, JTAG |
| Reel Size (in) | 13 |
| Reference Output | Yes |
| Requires Terms and Conditions | Does not require acceptance of Terms and Conditions |
| Spread Spectrum | Yes |
| Supply Voltage (V) | 3.3 - 3.3 |
| Tape & Reel | Yes |
| Thickness (mm) | 0.85 |
| Width (mm) | 6 |
| Xtal Freq (KHz) | 8 - 50 |
| Xtal Inputs (#) | 1 |
Description
The IDT5V9885T is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and
networking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
The IDT5V9885T can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in-system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
other four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.