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ECADモデルを調べる
概要
Description
The RC32012A regenerates and distributes ultra-low jitter clock outputs and features up to 4 independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLLs (DPLLs) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: IEEE 1588 clock synthesis; SyncE clock generation; jitter attenuation and radio clock generation including SYSREF generation for converters. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 56Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The device is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards and wireless small cell applications.
To see other devices in this product family, visit the ClockMatrix Timing Solutions page.
特長
- Two timing channels and four independent frequency domains
- Output jitter below 100fs RMS
- Digital PLLs (DPLLs) lock to any frequency from 0.5kHz to 1GHz
- DPLLs / Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
- DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
- Can be used as a jitter attenuator, clock generator, or synchronizer
- Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
- Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
- Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
- The device can configure itself automatically after reset via:
- Internal Customer-programmable One-Time Programmable memory
- Standard external I2C EPROM via separate I2C Master Port
アプリケーション
ドキュメント
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その他資料
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概要
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回路図
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設計・開発
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Evaluation Kit for RC38612 and RC32012 ClockMatrix
This is the evaluation kit for the Renesas RC38612 ClockMatrix Radio Access Network Equipment Synchronizer. This is the superset device and can also be used to evaluate...
主要ドキュメント:
モデル
ECADモデル
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製品選択
Processing table
| -40 to 85°C | Tray | サンプルを入手, | |
| -40 to 85°C | Reel |
Tips for Using This Parametric Table:
- Hide Filters button in header: Collapse or expands filters
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- Export button in header: Export the filtered results of the table to an Excel document
- Filter parts search bar in header: Type to filter table results by part number
- Hide column button in column headers: Select to hide columns in table
- AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
- Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
- Document icon next to product name in row: View the featured document for this product
- Chip icon next to the right of the document icon in row: View the block diagram for this product
- Cart icon to the right of the chip icon: Indicates that samples are available for this product
play_circle_filledビデオ&トレーニング
IDT ClockMatrix™ Timing Solution for 100Gbps Interface Speeds (IEEE 1588, OTN, and SyncE)
Introducing the IDT ClockMatrix™ family of devices - high-performance, precision timing solutions designed to simplify clock designs for applications with up to 100 Gbps interface speeds.
They can be used anywhere in a system to perform critical timing functions, such as clock generation, frequency translation, jitter attenuation and phase alignment. A range of devices in the family support BBU, OTN, SyncE, synthesizer and jitter attenuator applications with several density options for each.
For more information, visit www.idt.com/clockmatrix.
Video List
ニュース＆ブログ
| Benefits of a Point-of-Use Clock for Jitter Optimization | ブログ | 2021年4月27日 |
