概要

The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters (ADC) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input signal can also be used.
ADC1206S040H - Block Diagram
ADC1206S040H - Block Diagram
  • 12-bit resolution
  • -3 dB bandwidth of 245 MHz
  • 5 V power supplies and 3.3 V output power supply
  • Binary or twos complement CMOS outputs
  • Differential AC or Positive Emitter-Coupled Logic (PECL) clock input
  • TTL
  • compatible
  • Differential analog input
  • External amplitude range control
  • In-range CMOS compatible output
  • Integrated sample and hold amplifier
  • Low analog input capacitance (typical 2 pF), no buffer amplifier required
  • Power dissipation 550 mW (typical)
  • Sampling rate up to 70 MHz
  • TTL and CMOS compatible digital outputs
  • TTL and CMOS compatible static digital inputs
  • Voltage controlled regulator included

ドキュメント

タイトル 分類 日付
ADC1206S SER Datasheet
PDF1.31 MB
データシート
PDN# : DC-14-01 PRODUCT DISCONTINUANCE NOTICE
PDF538 KB
EOL通知

設計・開発

ソフトウェアダウンロード

タイトル 分類 日付
PDN# : DC-14-01 PRODUCT DISCONTINUANCE NOTICE
PDF538 KB
EOL通知

ボード＆キット

ADC1206S040 - Evaluation Board

ADC1206S040

Demonstration
ご購入

ADC1206S040 demo board

Our ADC demo board is suitable for dynamic performances evaluation.

主要ドキュメント:
ADC1206S Quick Start Guide

ECADモデル

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製品選択

    Processing table
    型名
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    ADC1206S040H-C1
    block_flippedEOL品
    memory
    view_in_ar
    		PQFP 44 I Yes Tray
    ADC1206S040H-C18
    block_flippedEOL品
    memory
    view_in_ar
    		PQFP 44 I Yes Reel
    Parametric Table tips

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