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Low Skew, 1-to-5, Differential-to-3.3V LVPECL/ECL Fanout Buffer

Package Information

Pitch (mm) 0.8
Lead Count (#) 32
Pkg. Type TQFP
Pkg. Dimensions (mm) 7.0 x 7.0 x 1.4
Pkg. Code PRG32

Environmental & Export Classifications

Moisture Sensitivity Level (MSL) 3
Pb (Lead) Free Yes
ECCN NLR
HTSUS 8542390001

Product Attributes

Pkg. Type TQFP
Lead Count (#) 32
Carrier Type Reel
Moisture Sensitivity Level (MSL) 3
Qty. per Reel (#) 2000
Qty. per Carrier (#) 0
Package Area (mm²) 49.0
Pitch (mm) 0.8
Pkg. Dimensions (mm) 7.0 x 7.0 x 1.4
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range -40 to +85°C
Advanced Features Feedback Input
C-C Jitter Max P-P (ps) 50
Core Voltage (V) 3.3
Feedback Input Yes
Function Buffer, Divider
Input Freq (MHz) 31.25 - 700
Input Type HCSL, HSTL, LVDS, LVPECL
Inputs (#) 2
Length (mm) 7
MOQ 2000
Output Banks (#) 1
Output Freq Range (MHz) 31.25 - 700
Output Skew (ps) 55
Output Type LVPECL
Output Voltage (V) 3.3
Outputs (#) 5
Prog. Clock No
Reel Size (in) 13
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel Yes
Thickness (mm) 1.4
Width (mm) 7

Description

The 8735BI-01 is a highly versatile 1:5 differential- to-3.3V LVPECL clock generator. The 8735BI-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier, or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider, and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, and 1:8. The external feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.