Overview

The 9DB436 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen 1–3 in zero delay mode and PCIe Gen 1–4 in fanout mode. The 9DB436 also features a Safe Power Sequence (SPS) clock input. The 9DB436 is a pin-compatible upgrade to the 9DB433 and 9DB434.

9DB436 - Block Diagram
9DB436 - Pinout
9DB436 - Safe Power Sequence Clock Input Diagram
9DB436 - Block Diagram
9DB436 - Pinout
9DB436 - Safe Power Sequence Clock Input Diagram
  • Four 0.7V current-mode differential HCSL output pairs
  • PCIe Gen 3 jitter < 0.6ps RMS in ZDB mode
  • PCIe Gen 4 additive jitter < 0.1ps RMS in fanout mode
  • SPS internal receiver bias network keeps the input clock parked when input is floating
  • Supports both 85Ω and 100Ω output impedance with appropriate resistor selection
  • OE# pins default to controlling outputs
  • Supports zero delay buffer mode and fanout mode
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs
  • Spread spectrum compatible
  • Three selectable SMBus addresses

Applications

  • Riser cards
  • Storage
  • Networking
  • JBOD

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    9DB436AGILF
    circleObsolete
    memory
    view_in_ar
    		TSSOP 28 I Yes Tube
    9DB436AGILFT
    circleObsolete
    memory
    view_in_ar
    		TSSOP 28 I Yes Reel
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    Videos & Training

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview
    Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems

    News & Blog Posts

    Blog Post Apr 14, 2022
    Blog Post May 22, 2018
    News Apr 30, 2018