Overview
Description
The 874003D-02 is a high performance Differential- to-LVDS Jitter Attenuator designed for use in PCI Express® systems. In some PCI Express® systems, such as those found in desktop PCs, the PCI Express® clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874003D-02 has a bandwidth of 2.1MHz. The 2.1MHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 874003D-02 uses IDT's 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express® add-in cards.
Features
- Three Differential LVDS output pairs
- One Differential clock input
- CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Output frequency range: 98MHz - 320MHz
- Input frequency range: 98MHz - 128MHz
- VCO range: 490MHz - 640MHz
- Cycle-to-cycle jitter: 35ps (maximum)
- Supports PCI Express® Spread-Spectrum Clocking
- The 2.1MHz bandwidth mode allows the system designer to make jitter attenuation/tracking skew design trade-offs
- 3.3V operating supply
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
Comparison
Applications
Documentation
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Type | Title | Date |
Datasheet | PDF 466 KB | |
Product Change Notice | PDF 611 KB | |
End Of Life Notice | PDF 161 KB | |
Product Change Notice | PDF 611 KB | |
Product Change Notice | PDF 596 KB | |
Product Change Notice | PDF 544 KB | |
Product Change Notice | PDF 95 KB | |
Product Change Notice | PDF 50 KB | |
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Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Videos & Training
This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
Watch the Video Series Below