The 8T49N241 and 8T49N242 generate up to 4 different output frequencies from two clock inputs and a Crystal input. Use the form below to configure the device.

NOTE: The 8T49N241 features fractional output dividers, allowing for any set of output frequencies up to 1 GHz.

Block Diagram


Timing Commander Configuration File Upload (optional)

Use this form to upload your Timing Commander configuration file for the 8T49N241 or 8T49N242. This will disable the configurator below. The datasheet addendum will be provided by Renesas after review.

Configuration File (.tcs) Uploader

General Configuration

Supply voltage of the device's core. Device Core Voltage
5 MSB of the device's I2C address. I2C Address
I2C interface speed. I2C Speed
EEPROM usage at power-up: Determines whether the configuration is loaded from an external EEPROM. If not, the configuration is loaded from the internal OTP ROM. Boot from EEPROM
OTP usage at power-up: Determines whether the full device configuration shall be loaded from the OTP ROM, or only the first 8 bits. Boot from OTP

Input Configuration

The device may act as a frequency synthesizer with the PLL generating its operating frequency from just the Xtal input. If you want to use CLK0 and/or CLK1 clock inputs, choose Jitter attenuator mode. Mode of Operation
Input CLK0 Input CLK1 Input XTAL Input
Input frequencies. Valid range for CLK0 and CLK1 is 0.008 MHz-to-875 MHz. Valid range for XTAL is 10 MHz-to-50 MHz. Frequency (MHz)
Selects whether the crystal source is a passive crystal or a crystal oscillator (XO). Crystal Source
Interrupt enables
Enables or disables interrupt status flag for PLL Loss of lock. PLL loss of lock
Enables or disables interrupt status flag for PLL in holdover status. PLL in holdover
Enables or disables interrupt status flag for Loss of signal on CLK0 input. Loss of signal on CLK0
Enables or disables interrupt status flag for Loss of signal on CLK1 input. Loss of signal on CLK1

Output configuration

Q0 output Q1 output Q2 output Q3 output
Selects the default status of the output (on or off) at startup. This status can be modified in operation by I2C or GPIO (if applicable). Enable/Disable
Clock source selection for output pair Q2 or Q3: PLL, CLK0, CLK1 or XTAL input. Do not select CLK0 or CLK1 if the corresponding input frequency is faster than 250 MHz. CLK SEL PLL PLL
Output frequency. Valid range is 0.008 MHz-to-250 MHz for LVCMOS output, 0.008 MHz-to-1000 MHz for differential outputs. Frequency
Selects output type. High impedance (Hi-Z) disables the output. Output signal type
Selects the output signal level. VCCO
Selects the polarity of clock outputs (normal or inverted). Polarity

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The desired frequency set can be generated by: 8T49N241 8T49N242
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GPIO configuration

Selects the GPIO type: input or output. Type
Selects the function of the GPIO. Each GPIO has different functions. Please refer to the device datasheet for details. Function

Project information

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