Overview

The 9DMV0131 is a member of Renesas' SOC-Friendly 1.8 V Very-Low-Power (VLP) PCIe Gen1–5 family. The output has an OE# pin for optimal system control and power management. The part provides asynchronous or glitch-free switching modes.

9DMV0131 Block Diagram
9DMV0131 Pinout Diagram
9DMV0131 Block Diagram
9DMV0131 Pinout Diagram
  • LP-HCSL output; saves 2 resistors compared to standard HCSL output
  • 1.8 V operation; 12 mW typical power consumption
  • Selectable asynchronous or glitch-free switching; allows the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode
  • Spread spectrum compatible; supports EMI reduction
  • OE# pin; supports DIF power management
  • HCSL differential inputs; can be driven by common clock sources
  • 1 MHz to 200 MHz operating frequency
  • Space saving 3x3 mm 16-pin VFQFPN; minimal board space

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Price (USD) | 1ku
    Buy / Sample
    Part Number
    9DMV0131BKILF
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    view_in_ar
    Samples Available
    		 VFQFPN 16 I Yes Tray 2.414 Get Samples,
    9DMV0131BKILFT
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    memory
    view_in_ar
    		VFQFPN 16 I Yes Reel
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    Videos & Training

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview