概要
説明
The RC32508A regenerates and distributes ultra-low jitter clock outputs and features up to two independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLL (DPLL) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for clock generation and jitter attenuation for high-speed serial links. Input-to-input, input-to-output, and output-to-output phase skew can all be precisely managed. The device outputs ultra-low jitter clocks that can directly synchronize SerDes running at up to 112Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The device is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards, and OTN applications.
特長
- Can be configured as a clock generator or jitter attenuator/synchronizer
- Low power, less than 0.8W typical
- Low jitter, less than 50fs-RMS
- Compliant with ITU-T G.8262 & G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter
- Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz
- Up to 2 independent frequency domains and 8 integer output dividers
- Each frequency domain can be slaved with DPLL or free-run
- DPLL can be configured as DCO
- LVCMOS, AC-LVPECL, AC-LVDS, HCSL, and AC-CML output modes supported with programmable output swing
- Up to 2 single-ended or 1differential clock inputs, 1 crystal/XO/TCXO/OCXO input
- Supports 1MHz I²C, 400kHz SMBus or 50MHz SPI serial port
- Internal non-volatile memory (up to 8 different configurations) provides default device settings on power up.
- 1.8V core and output operation
- -40 °C to +85 °C industrial temperature operation
製品比較
アプリケーション
設計・開発
ソフトウェア／ツール
ソフトウェア／ツール
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会社名
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Software Package | ルネサス |
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ボード＆キット
Evaluation
RC32508A-EVK
アクティブ
FemtoClock™ 2 Evaluation Kit
This is the evaluation kit for the RC32508A jitter attenuator and clock generator. The board comes populated with an RC32508A device.
Recommended Documents:
モデル
ECADモデル
SamacSysの回路図シンボル、PCBフットプリント、および3D CADモデルは、製品オプションテーブルのCADモデルリンクをクリックすることで参照できます。シンボルまたはモデルが対応していない場合は、SamacSysに直接リクエスト可能です。
製品選択
適用されたフィルター
ビデオ&トレーニング
Lab on the Cloud Demo for FemtoClock®2 Ultra-Low Phase Noise Synthesizer and Jitter Attenuator
Demonstration of Renesas’ Lab on the Cloud virtual environment for FemtoClock®2 ultra-low phase noise synthesizer and jitter attenuator.
Video List
