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3.3V Zero Delay Clock Buffer, Spread Spectrum Compatible

パッケージ情報

Pitch (mm) 0.65
Lead Count (#) 16
Pkg. Type TSSOP
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0
Pkg. Code PGG16

環境及び輸出分類情報

Moisture Sensitivity Level (MSL) 1
Pb (Lead) Free Yes
ECCN (US) NLR
HTS (US) 8542390001

製品スペック

Pkg. Type TSSOP
Lead Count (#) 16
Carrier Type Tube
Moisture Sensitivity Level (MSL) 1
Qty. per Carrier (#) 96
Package Area (mm²) 22.0
Pitch (mm) 0.65
Pkg. Dimensions (mm) 5.0 x 4.4 x 1.0
Qty. per Reel (#) 0
Pb (Lead) Free Yes
Pb Free Category e3 Sn
Temp. Range 0 to 70°C
Price (USD) | 1ku 1.7776
Accepts Spread Spec Input Yes
Advanced Features Accepts Spread Spec Input
C-C Jitter Max P-P (ps) 200
Core Voltage (V) 3.3
Input Freq (MHz) 10 - 133
Input Type LVCMOS
Inputs (#) 1
Length (mm) 5
MOQ 288
Multiply/Divide Value 1.00000
Output Banks (#) 2
Output Freq Range (MHz) 10 - 133
Output Skew (ps) 250
Output Type LVCMOS
Output Voltage (V) 3.3
Outputs (#) 9
Requires Terms and Conditions Does not require acceptance of Terms and Conditions
Tape & Reel No
Thickness (mm) 1
Width (mm) 4.4

説明

The 23S09 is a high-speed phase-locked loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10MHz to 133MHz. The device is a 16-pin version of the 23S05.

The 23S09 accepts one reference input and drives two banks of four low-skew clocks. The -1H version of this device operates up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the 23S09 enters power down. In this mode, the device will draw less than 12μA for the commercial temperature range and less than 25μA for the industrial temperature range, and the outputs are tri-stated. This device is characterized for both industrial and commercial operation.