Overview

The 9DS400 is a 4-output PCIe PLL with the ability to inject spread spectrum onto the incoming differential clock, while maintaining good phase noise.

9DS400 - Block Diagram
9DS400 - Pinout
9DS400 - Block Diagram
9DS400 - Pinout
  • 4- 0.7V current-mode differential output pairs
  • Supports Spread Injection mode and fanout mode
  • Two pin selectable down spread amounts: 0.5% and 0.25%
  • 50-110 MHz operation in PLL mode
  • 50-400 MHz operation in Bypass mode
  • Bypass mode
  • Supports undriven differential outputs in PD# and SRC_STOP# modes for power management
  • Output cycle-cycle jitter < 50ps
  • Output to Output skew <50ps
  • Phase jitter: PCIe Gen1 < 86ps peak to peak
  • Phase jitter: PCIe Gen2 < 3.0/3.1ps rms

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    9DS400AGLF
    circleObsolete
    memory
    view_in_ar
    		TSSOP 28 C Yes Tube
    9DS400AGLFT
    circleObsolete
    memory
    view_in_ar
    		TSSOP 28 C Yes Reel
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    Videos & Training

    PCIe Clocking Architectures (Common and Separate)

    This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

    Watch the Video Series Below

    Video List
    PCIe Clocking Architectures (Common and Separate)
    PCIe Common Clock Architecture and its Impact on Clocking
    PCIe Separate Reference without Spread Clock Architecture
    PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview