New V3M Starter Kit with high performance and low power consumption will be available from September 2018 onwards

Software development for ADAS and AD applications is increasing in scale and complexity in recent years, in order to accelerate the development of autonomous driving and to develop new functionality to attractively differentiate vehicles. Renesas has developed R-Car Starter Kits for supporting automotive software development.


The V3M Starter Kit simplifies and accelerates the development of New Car Assessment program (NCAP, Note 1), front camera applications, surround view systems, and lidars. The Starter Kit is based on the R-Car V3M image recognition system-on-chip (SoC), delivering a combination of low power consumption and high performance for the growing NCAP front camera market.


The R-Car V3M Starter Kit, the R-Car V3M SoC, and supporting software and tools including Renesas' open-source e2 studio IDE integrated development environment (IDE), are part of the open, innovative, and trusted Renesas autonomy™ Platform that delivers end-to-end solutions for advanced driver assistance systems (ADAS) and automated driving.

The Starter Kit is a ready-to-use kit including the required interface and tools. The integrated 440-pin expansion port gives full freedom for system manufacturers to develop application specific expansion boards for a wide range of computing applications, from a simple advanced computer vision development environment to prototyping of multi-camera systems for applications such as surround view. This flexibility of the board reduces the time needed for hardware development while maintaining a high degree of software portability and reusability.

The R-Car V3M Starter Kit is supported by a Linux BSP, which is available through elinux.org. Further commercial operating systems will be made available from next year onwards.

(Note 1) New Car Assessment Program (NCAP): A government car safety program tasked with evaluating new automobile designs for performance against various safety threats.

Connectors Placement top view

Figure 1. Connectors Placement top view.

Connectors Placement bottom view

Figure 2. Connectors Placement bottom view.

Product Specifications

Class Function On-board At CoM Express connector
CPU Arm® CA53
(Arm® v8)
800 MHz dual core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K -
Arm® CR7
(Arm® v7)
800 MHz, with VFPv3, L1$ I/D 32K/32K, I/D-TCM 32K/32K, lock-step -
Memory SoC Internal 448KBytes System RAM -
DDR 2 GBytes (6.4 GBytes/s)
DDR3L-1600, 32-bit wide
-
HyperFlash
(bootable)
64 MiBytes Hyper Flash (RPC, reduced pin-count)
(512 Mbits, 160 MHz, 320 MBytes/s)
alternatively to on-board Hyper/QSPI flash memory: 2ch QSPI (max. 80 MHz, 80 MBytes/s)
QSPI Flash
(bootable)
64MiBytes QSPI (512 Mbits, 80 MHz, 80 MBytes/s)
eMMC 32GiBytes eMMC (HS200) [available only for PCB V3.00 and later] available
Parallel SRAM/ROM
(bootable)
- available (shared with many other functions)
Video out HDMI no native HDMI; derived from LVDS by converter
HDMI connector (type A, 19 pins)
HDMI 1.4, up to 1080p60, 165MHz, (no audio)
alternatively to on-board connector (shared with trace and LVDI)
RGB
(parallel)
- RGB888 (shared with many other functions)
LVDS - 1 channel (4+1CLK differential pairs) TIA/EIA-644, max 148.5MHz, (shared with trace and HDMI)
Video in Serial - MIPI-CSI2, 1 channel (4-lanes)
VC/DT supported, up to 1.5Gbps/lane
Parallel - 2 channels, RGB/YCbCr/Raw, max 100 MHz
(shared with many other functions)
Interface EthAVB PHY + RJ45 connector (100/1000) alternatively to on-board PHY: RGMII V1.3 interface (2.5V)
SCIF 1 channel via Mini-USB-B (via FT232 USB-to-UART bridge) up to 3 additional channels (shared)
(on-board channel optionally)
HSCIF - up to 4 channels (shared)
MSIOF (SPI) - up to 3 channels (SPI/IIS, master/slave, 66MHz) (shared)
CAN-FD - up to 2 channels, 8Mbps (shared)
I2C for on-board peripherals up to 5 channels, 400kHz, master/slave (shared)
DigRF - available
Timer PWM - up to 5 channels (shared)
HMI output 3 LEDs at GPIOs -
input 4 DIP-switches at GPIOs
8 DIP-switches at CPLD
-
ADC   - 8 channels, 12-bit
GPIOs   - 14 GPIOs by default, up to 105 GPIOs (shared)
Reset   Reset button (and LED) input and output
Power   5V/3A input
PMIC for all required voltages (OTP)
power-up/down signals
power-good status
Boot
Source
  HyperFlash, QSPI, SCIF, JTAG debugger QSPI Flash, SCIF, JTAG debugger, parallel ROM
Debug IF JTAG debug 20-pin (2.54mm) ARM_EML ("Lauterbach") available
JTAG trace ETM-A53-16K/R7-4K available
Parallel trace On-board connector for LVDS pod (shared with LVDS) available (shared with LVDS and HDMI)
Clocks   All necessary clocks on-board -
Mode   Can be configured by CPLD, DIPSW, USB or software -
Cooling   Heat-sink and fan -
Expansion   - CoM Express connector (440-pin) backwards-compatible to H3 Starter Kit
Interrupts   - NMI, IRQ on GPIOs
Size   95 x 95mm (equivalent to CoM Express type 6) -
SoC   Soldered -

R-Car Starter & Solution Kits