High-end MCU designed especially for electronic power steering systems, supporting the new CAN-FD communication standard
The RH850/P1M-E microcontroller is the successor of the successful RH850/P1M series, supporting now also the CAN-FD.Like its predecessor, the RH850/P1M-E has been designed for systems with ASIL-D safety level, featuring many safety functions such as lockstep CPU, ECC, and BISTs (Built-in Self Tests). Along with a variety of interfaces (e.g. SENT a digital i/f for sensors) it also has a dedicated security module(ICU-S), implemented in hardware, to protect sensitive data like secret keys. With its low power consumption, the MCU is well suited for today’s requirements regarding energy efficient ECUs in automotive area.
Main Solutions
Key Features:
| ITEM | RH850/P1M-E | ||||
|---|---|---|---|---|---|
| Pin-Count | 100-pin | 144-pin | |||
| CPU | CPU System | RH850G3M (With Lockstep) | |||
| CPU Frequency | 160 MHz (Main oscillator 16 MHz) | ||||
| Memory Protection Unit (MPU) |
16 areas | ||||
| Floating Point Unit (FPU) |
Single precision and double precision | ||||
| Memory | Program Flash | 1 MB to 2 MB | |||
| Data Flash | 32 KB (Flash 1 MB products) / 64 KB (Flash 2 MB products) | ||||
| RAM | Local RAM | 128 KB | |||
| Global RAM | 64 KB | ||||
| Trace RAM | 32 KB | ||||
| Emulation RAM | 8 KB (Flash 1 MB products) / 32 KB (Flash 2 MB products) | ||||
| Instruction Cache | 16 KB 4 way | ||||
| INTC | INTC1 (CPU core) | 32 channels (Redundant) | |||
| INTC2 | 352 channels | ||||
| DMA | DMA Controller (DMAC) |
16 channels (Redundant) | |||
| DTS | 128 channels (Redundant) | ||||
| Safety | Error Control Module (ECM) | Supported | |||
| Core Voltage Monitor （CVM） | Supported | ||||
| Built-in Self Test (BIST) with status flag | Supported | ||||
| ERROROUT | Supported | ||||
| Clock Monitor | Supported | ||||
| A/D Converter |
12-bit Resolution | 2 units (19 channels) | 2 units (24 channels) | ||
| Temperature Sensor | Supported | ||||
| Analog Input | ADCG0 | 9 channels | 12 channels | ||
| ADCG1 | 10 channels | 12 channels | |||
| Track and Hold | ADCG0 | 6 | |||
| ADCG1 | 4 | ||||
| Timers | 16-bit Timer Array Unit (TAUD) |
3 units | |||
| 32-bit Timer Array Unit (TAUJ) |
3 units | ||||
| Motor Control Timer (TSG3) |
2 units | ||||
| Timer Option Unit (TAPA) | 4 units (Hi-Z Control) | ||||
| Encoder Timer (ENCA) | 2 units | ||||
| Timer for Operating System (OSTM) |
7 units (Including 2 units for output) | ||||
| Watchdog Timer (WDTA) | 1 unit | ||||
| Timer Pattern Buffer (TPBA) |
2 units | ||||
| Peripheral Interconnect（PIC） | Supported | ||||
| Clock out | Supported | ||||
| Serial Interface | CANFD (RS-CANFD) | 3 channels | |||
| FlexRay | 2 channels | ||||
| Peripheral Sensor Interface 5(PSI5) | 2 channels | ||||
| Single Edge Nibble Transmission (RSENT) | 5 channels | 6 channels | |||
| Sync/Async USART (SCI3) | 3 channels | ||||
| LIN Master & UART (RLIN3) | 2 channels | ||||
| Clocked Serial Interface (CSIG) | 1 channel | ||||
| Queued Clocked Serial Interface (CSIH) | 4 channels | ||||
| Data CRC | 4 channels | ||||
| Security | Supported (ICU-S) | ||||
| Debug | Nexus-JTAG | Supported | |||
| LDU | Supported | ||||
| Trace RAM | Supported | ||||
| Measurement (Memory Read) | Supported | ||||
| Operating Temperature (Junction) | Tj = -40 to 150 ℃ | ||||
| Operating Voltage Operating Voltage | 3.0V to 5.5V (Built in voltage regulator for core) | ||||
| 3.0 to 5.5 V (For I/O) / 1.25 V (For core) | |||||
Block Diagram:
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