The 8L3010I is a low skew, 1-to-10 LVCMOS / LVTTL Fanout Buffer. The low impedance LVCMOS/LVTTL outputs are designed to drive 50? series or parallel terminated transmission lines. The 8L3010I is characterized at full 3.3V and 2.5V, mixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 2.5V/1.8V and 2.5V/1.5V output operating supply modes. The input clock is selected from two differential clock inputs or a crystal input. The differential input can be wired to accept a single-ended input. The internal oscillator circuit is automatically disabled if the crystal input is not selected.

Features

  • Ten LVCMOS / LVTTL outputs up to 200MHz
  • Differential input pair can accept the following differential input levels: LVPECL, LVDS, HCSL
  • Crystal Oscillator Interface
  • Crystal input frequency range: 10MHz to 40MHz
  • Output skew: 50ps (maximum) @ 3.3V/3.3V
  • Additive RMS phase jitter: 0.24ps (typical) @ 3.3V/3.3V
  • Synchronous output enable to avoid clock glitch
  • Power supply modes: Core / Output 3.3V / 3.3V 2.5V / 2.5V 3.3V / 2.5V 3.3V / 1.8V 3.3V / 1.5V 2.5V / 1.8V 2.5V / 1.5V
  • 5V input tolerance
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Part Number Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8L3010ANLGI
Active VFQFPN 32 I Yes Tray
Availability
8L3010ANLGI8
Active VFQFPN 32 I Yes Reel
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
8L3010 Datasheet Datasheet PDF 548 KB
Application Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCNs & PDNs
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location Product Change Notice PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : W1308-01 Change of Passivation Thickness Product Change Notice PDF 941 KB
Other
Clock Distribution Overview 日本語 Overview PDF 217 KB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB